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INTEGRATED CIRCUITS
DATA SHEET
SAA7215; SAA7216; SAA7221 Integrated MPEG AVGD decoders
Preliminary specification Supersedes data of 1998 Sep 11 File under Integrated Circuits, IC02 2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
FEATURES General features * Integrated MPEG AVGD decoder: audio, video and graphics decoding and digital video encoding * 5 planes display chain: background colour, background plane, MPEG display plane, graphics plane and cursor plane * 16-Mbit or 32-Mbit external Synchronous DRAM (SDRAM) for MPEG audio and video decoding and graphics data storage * Single or double external SDRAM organized as 1 M x 16 or 2 x 1 M x 16 (two independent 16-bit data bus) interfacing at 81 MHz. Due to efficient memory use in MPEG decoding, more than 1 Mbit is available for graphics in the single SDRAM configuration whereas 17 Mbits are available in the double SDRAM configuration. * All basic operations of the AVGD decoder are possible in both 16- and 32-Mbit configuration; enhanced performance is achieved by the use of 32-Mbit external SDRAM * Targeted to BSkyB 3.0 and Canal+ basic box and web box specifications * Fast 16-bit data + 22-bit address synchronous or asynchronous interface with external controller at up to 40.5 MHz * Dedicated input for compressed audio and video in Packetized Elementary Stream (PES) or Elementary Stream (ES) in byte wide or bit serial format. Accompanying strobe signals distinguish between audio and video data. Transport stream error correction available. * Audio and/or video can also be input via the CPU interface in PES or ES in 8 or 16-bit parallel format * Single 27 or 40.5 MHz external clock for time base reference and internal processing. Internal system time base at 90 kHz can be synchronized via CPU port. All required decoding and presentation clocks are generated internally. * Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks * Optimum compatibility with T-MIPS controller family (SAA7214, SAA7219 and successors) * Boundary scan testing implemented * External SDRAM self test * Supply voltage: 3.3 V; package: SQFP208. 2000 Jan 31 2
SAA7215; SAA7216; SAA7221
CPU related features * 16-bit data, 22-bit address, Chip Select, Data Strobe and DaTa ACKnowledge external control protocol * Fast 16-bit data plus 22-bit address synchronous interface with the SAA7214, SAA7219 family at up to 40.5 MHz * Asynchronous interface possible with external microcontroller * Support of fast DMA transfer * Flexible bidirectional interface to external SDRAM * High speed/low latency interface with second graphics SDRAM * Byte access to the full SDRAM in the upper 16-Mbit address range * Independent memory mapping of SDRAM and control registers * Two programmable independent interrupt lines available * Supports Motorola 68xxx interfaces as well as LSI L64108 interface. MPEG-2 system features * Parsing of MPEG-2 PES and MPEG-1 packet streams * Double system time clock counters * Stand-alone or supervised audio/video synchronization * Processing of errors flagged by channel decoding section. MPEG-2 video features * Decoding of MPEG-2 video up to main level, main profile * Output picture format: CCIR-601 4 : 2 : 2 interlaced pictures. Picture format 720 x 576 at 50 Hz or 720 x 480 at 60 Hz. * Support of constant and variable bit rates up to 15 Mbits/s for the elementary stream * Horizontal and vertical pan and scan allows the extraction of a window from the coded picture * Flexible horizontal scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies; in case of shrinking an anti-aliasing pre-filter is applied
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
* Vertical scaling with fixed factors 0.5, 0.75, 1 or 2; factor 0.5 realizes picture shrink. Factor 2 can be used for up-conversion of pictures with 288 (240) lines or less; factor 0.75 is used for letterbox presentation. * Horizontal and vertical scaling can be combined to scale pictures to 14 of their original size, thus freeing up screen space for graphic applications like electronic program guides * Non full screen MPEG pictures can be displayed in a box of which position and background colour are adjustable by the external microcontroller; structured background is available as part of the graphic features * Nominal video input buffer size for MP at ML 2.7-Mbit * Video output may be slaved to internally (master) generated or externally (slave) supplied HV synchronization signals or CCIR-656 contained synchronization signals. The position of active video is programmable. Display phase is not affected by MPEG timebase changes. * Decoding and presentation can be independently handled under CPU control * Various trick modes under control of external microcontroller: - Freeze field/frame on I- or P-frames; restart on I-picture - Freeze field on B-frames; restart at any moment - Scanning and decoding of I- or I- and P-frames in a IBP sequence - Single step mode - Repeat/skip field for time base correction - Repeat/skip frame for display parity integrity. * Synchronization modes: DTS controlled, DTS free running, software controlled, buffer controlled * DTS register can be set via external controller; programmable processing delay compensation. MPEG-2 audio features * Supported audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 kHz * Independent channel volume control and programmable inter-channel crosstalk through a baseband audio processing unit * MPEG audio decoder - Decoding of 2 channels, layer I and II MPEG-1 audio and low sampling frequency extension of MPEG-2 - Supports for mono, stereo, intensity stereo and dual channel mode 2000 Jan 31 3
SAA7215; SAA7216; SAA7221
- CRC error detection with automatic mute - Constant and variable bit rates up to 448 kbit/s - Selectable output channel in dual channel mode - Storage of last 54 bytes in ancillary data field - Dynamic range control at output. * Muting possibility via external controller; automatic muting in case of errors * Generation of `beeps' with programmable tone height, duration and amplitude * Linear PCM decoding - Support for up to 8 channels linear PCM elementary audio streams - Supports for 8, 16, 20 and 24 bit/sample - Supports for bit rates up to 6.144 Mbit/s - 96 kHz LPCM samples will be mapped to a 48 kHz multi-channel format - Volume control for linear PCM samples in three steps: -6, -12 and -18 dB. * Burst-formatting for interconnection with an external multi-channel decoder - AC-3 elementary streams (IEC1937) - MPEG-2 multi-channel streams in ES or PES format - Output via the digital audio output or the IEC 958 output. * Output stage - Global control for volume and balance - Serial multi-channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible either to I2S or Japanese formats; output can be set to high impedance mode via the external controller - IEC958 (Serial SPDIF) audio output; output can be set to high impedance mode - Clock output 256 or 384 x fs for external DA converter or clock input; output can be set to high impedance mode. * Audio FIFO in external SDRAM; programmable buffer size, at least 64 kbit is available * Synchronization modes: PTS controlled, PTS free running, software controlled, buffer controlled * PTS register can be set via external controller; programmable processing delay compensation. Background colour * 24 bit YCbCr colour.
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
Graphics features 2 nearly identical graphics planes: the first graphics plane commonly called the background plane and the second graphics plane commonly called foreground plane. The following features apply for both planes. * Graphics is presented in boxes independent of video format * Boxes can be up to full screen allowing double buffer display mechanism * Two independent data paths with RGB 4 : 4 : 4 and YCbCr 4 : 2 : 2 formats available with independent mixing * RGB path transparent to YCbCr format * Conversion matrices available to allow any format on any different data path (RGB or YCbCr) * Screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling, overlapping and fading of regions * Real-time anti-flickering performed in hardware; programmable hardware available for off-line anti-flickering * Hard edged or soft edged wiping of regions available * Support of 2, 4, 8, 16 bit/pixel in fixed bit maps format or coded in accordance to the DVB variable/run length standard for region based graphics * Chrominance down-sampling filter switched per region * Display colours are obtained via colour look up tables or directly from bitmap; CLUT output can be YCbCrT at 8-bit for each signal component thus enabling 16 M different colours and 6-bit for T which gives 64 mixing levels with video; CLUT output can also be RGBT with same resolutions; non linear processing available by means of LUTs * Map table mechanism to specify a sub set of entries if the CLUT is larger than required by the coded bit pattern; supported map tables are 16 to 256, 4 to 256 and 4 to 16 * Up to 4 graphics boxes may overlap vertically even inside one graphics layer thanks to the use of flexible chained descriptors * Graphics mechanism can be used for signal generation in the vertical blanking interval; useful for teletext, wide screen signalling, closed caption etc.
SAA7215; SAA7216; SAA7221
In addition to the previous listed features, the second graphics plane sustains: * Teletext insertion with automatic teletext data retrieving from the external SDRAM. Data manipulation unit * Powerful 3D block move with different patterns for source and destination area * Dedicated events for video synchronization * Scaling, format conversion and bit manipulation from a chained list of instructions. Cursor * Size of 1024 pixels * Programmable shape (8 x 128, 16 x 64, 32 x 32, 64 x 16 and 128 x 8) * 16 colours available with a 4 level transparency mixing with video and graphics * Cursor colours obtained via two 16 entry CLUTs with YCbCrT at 6, 4, 4 respectively 2 bits and RGBT at 4, 4, 4 respectively 4 bits (or 4, 5, 3, respectively 4 bits) * Cursor can be moved freely across the screen without overlapping restrictions. Digital output * Programmable selection for the mixed graphics planes with video for the CVBS and RGB outputs * Digital video input/output interface on 8 bit, 27 MHz (CbYCrY multiplexed bus), at a CCIR-656 format. Analog output * Analog video output interface on both the RGB and Y/C/CVBS formats available simultaneously * PAL/NTSC/SECAM encoding (SAA7221HS only) * Two DACs for CVBS, Y and C, CVBS running at 27 MHz 10-bit resolution * Three DACs for R (Y), G (Cb) and B (Cr) running at 27 MHz; 9-bit resolution connected to a 10-bit input DAC * Closed captioning and teletext encoding on CVBS * Macrovision 7.01 and 6.1 encoding capability on Y or CVBS and C or CVBS (SAA7216HS only).
2000 Jan 31
4
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
APPLICATIONS The SAA7215 integrated MPEG AVGD decoder is aimed at being used in MPEG digital TV applications. This decoder is primarily designed to be connected to a SAA7214 transport stream descrambler/demultiplexer/ microcontroller by means of glueless interfaces even though connections to other market demultiplexers and/or microcontrollers are possible. Compatibility is also targeted with the SAA7219 and with the successor of the T-MIPS family. The SAA7215 can be used in any system where high-end graphics are needed (associated SDRAM can be extended to 32-Mbit) as well as in low cost systems (all functions can be enabled with only 16-Mbit of associated SDRAM). Table 1 Possible options TYPE NUMBER SAA7215HS/C2 SAA7216HS/C1 SAA7221HS/C1 QUICK REFERENCE DATA SYMBOL VDD IDD CLK PARAMETER functional supply voltage range total supply current; VDD = 3.3 V MACROVISION no yes no
SAA7215; SAA7216; SAA7221
GENERAL DESCRIPTION The SAA7215HS, SAA7216HS, SAA7221H is a MPEG-2 source decoder which combines audio decoding and video decoding. Additionally to these basic MPEG functions it also provides means for enhanced graphics, background display and/or on-screen display as well as encoding of output video. Due to an optimized architecture for audio and video decoding, maximum capacity in external memory and processing power from the external CPU is available for graphics support. Possible options are indicated in Table 1.
SECAM no no yes
MIN. 3.0 - -30 ppm -30 ppm
TYP. 3.3 tbf +27 +40.5 -
MAX. 3.6 +30 ppm +30 ppm V
UNIT mA MHz MHz
device clock input frequency (2 solutions are possible)
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7215HS/C2 SAA7216HS/C1 SAA7221HS/C1 SQFP208 DESCRIPTION plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm VERSION SOT316-1
2000 Jan 31
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
BLOCK DIAGRAMS
SAA7215; SAA7216; SAA7221
handbook, full pagewidth
16-Mbit SDRAM (compulsory)
16-Mbit SDRAM (optional)
MEMORY INTERFACE 1
MEMORY INTERFACE 2
MPEG data
AUDIO/VIDEO INTERFACE
DATA MANIPULATION UNIT
SYSTEM TIME BASE UNIT VIDEO INPUT BUFFER & SYNCHRONIZATION
data
data
DIGITAL ENCODER
analog video
DIGITAL VIDEO SYNCHRONIZATION
digital video
VIDEO DECODER CURSOR UNIT AUDIO INPUT BUFFER & SYNCHRONIZATION GRAPHICS UNIT 2
audio DACs
AUDIO DECODER
CLK
CLOCK GENERATION
GRAPHICS UNIT 1
control
JTAG
DISPLAY UNIT
CPU
HOST INTERFACE
FCE107
Fig.1 Block diagram.
2000 Jan 31
6
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
handbook, full pagewidth
16-Mbit SDRAM
MEMORY INTERFACE 1
MEMORY INTERFACE 2
MPEG data
AUDIO/VIDEO INTERFACE
DATA MANIPULATION UNIT
SYSTEM TIME BASE UNIT VIDEO INPUT BUFFER & SYNCHRONIZATION
data
DIGITAL ENCODER
analog video
DIGITAL VIDEO SYNCHRONIZATION
digital video
VIDEO DECODER CURSOR UNIT AUDIO INPUT BUFFER & SYNCHRONIZATION GRAPHICS UNIT 2
audio DACs
AUDIO DECODER
CLK
CLOCK GENERATION
GRAPHICS UNIT 1
control
JTAG
DISPLAY UNIT
CPU
HOST INTERFACE
FCE108
Fig.2 Block diagram with preferred use in 16-Mbit configuration.
2000 Jan 31
7
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
handbook, full pagewidth
16-Mbit SDRAM (MPEG)
16-Mbit SDRAM (Graphics)
MEMORY INTERFACE 1
MEMORY INTERFACE 2
MPEG data
AUDIO/VIDEO INTERFACE
data data
DATA MANIPULATION UNIT
SYSTEM TIME BASE UNIT VIDEO INPUT BUFFER & SYNCHRONIZATION
DIGITAL ENCODER
analog video
DIGITAL VIDEO SYNCHRONIZATION
digital video
VIDEO DECODER CURSOR UNIT AUDIO INPUT BUFFER & SYNCHRONIZATION GRAPHICS UNIT 2
audio DACs
AUDIO DECODER
CLK
CLOCK GENERATION
control
GRAPHICS UNIT 1
JTAG
DISPLAY UNIT
CPU
HOST INTERFACE
FCE109
Fig.3 Block diagram with preferred use in 32-Mbit configuration.
2000 Jan 31
8
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PINNING Pinning table (listed numerically) SYMBOL VSS DATA(4) DATA(5) DATA(6 DATA(7) DATA(8) DATA(9) VDD DATA(10) DATA(11) DATA(12) DATA(13) DATA(14) DATA(15) VSS SDRAM_ADDR1(3) SDRAM_ADDR1(2) SDRAM_ADDR1(4) SDRAM_ADDR1(1) SDRAM_ADDR1(5) SDRAM_ADDR1(0) VDD SDRAM_ADDR1(6) SDRAM_ADDR1(10) SDRAM_ADDR1(7) VSS(CO) VDD(CO) SDRAM_ADDR1(11) SDRAM_ADDR1(9) SDRAM_ADDR1(8) VSS SDRAM_UDQ1 SDRAM_RAS1 SDRAM_CAS1 SDRAM_WE1 VDD SDRAM_DATA1(8) SDRAM_DATA1(7) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TYPE(1) S I/O I/O I/O I/O I/O I/O S I/O I/O I/O I/O I/O I/O S O O O O O O S O O O S S O O O S O O O O S I/O I/O ground for pad ring
SAA7215; SAA7216; SAA7221
DESCRIPTION CPU data input or output (bit 4); note 2 CPU data input or output (bit 5); note 2 CPU data input or output (bit 6); note 2 CPU data input or output (bit 7); note 2 CPU data input or output (bit 8); note 2 CPU data input or output (bit 9); note 2 supply voltage for pad ring CPU data input or output (bit 10); note 2 CPU data input or output (bit 11); note 2 CPU data input or output (bit 12); note 2 CPU data input or output (bit 13); note 2 CPU data input or output (bit 14); note 2 CPU data input or output (bit 15); note 2 ground for pad ring SDRAM address 1 output (bit 3) SDRAM address 1 output (bit 2) SDRAM address 1 output (bit 4) SDRAM address 1 output (bit 1) SDRAM address 1 output (bit 5) SDRAM address 1 output (bit 0) supply voltage for pad ring SDRAM address 1 output (bit 6) SDRAM address 1 output (bit 10) SDRAM address 1 output (bit 7) ground for core logic supply voltage for digital core logic SDRAM address 1 output (bit 11) SDRAM address 1 output (bit 9) SDRAM address 1 output (bit 8) ground for pad ring SDRAM write mask 1 output SDRAM row address strobe 1 output SDRAM column address 1 output SDRAM write enable 1 output supply voltage for pad ring SDRAM data 1 input or output (bit 8) SDRAM data 1 input or output (bit 7)
2000 Jan 31
9
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
SYMBOL SDRAM_DATA1(9) SDRAM_DATA1(6) SDRAM_DATA1(10) SDRAM_DATA11(5) VSS SDRAM_DATA1(11) SDRAM_DATA1(4) SDRAM_DATA1(12) SDRAM_DATA1(3) SDRAM_DATA1(13) SDRAM_DATA1(2) VDD SDRAM_DATA1(14) SDRAM_DATA1(1) SDRAM_DATA1(15) SDRAM_DATA1(0) READ_OUT1 READ_IN1 VSS CP81MEXT CP81M VDD READ_IN2 READ_OUT2 SDRAM_DATA2(0) SDRAM_DATA2(15) SDRAM_DATA2(1) SDRAM_DATA2(14) VSS SDRAM_DATA2(2) SDRAM_DATA2(13) SDRAM_DATA2(3) SDRAM_DATA2(12) SDRAM_DATA2(4) SDRAM_DATA2(11) VDD SDRAM_DATA2(5) SDRAM_DATA2(10) SDRAM_DATA2(6) VSS(CO) VDD(CO) 2000 Jan 31
PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
TYPE(1) I/O I/O I/O I/O S I/O I/O I/O I/O I/O I/O S I/O I/O I/O I/O O I S I O S I O I/O I/O I/O I/O S I/O I/O I/O I/O I/O I/O S I/O I/O I/O S S
DESCRIPTION SDRAM data 1 input or output (bit 9) SDRAM data 1 input or output (bit 6) SDRAM data 1 input or output (bit 10) SDRAM data 1 input or output (bit 5) ground for pad ring SDRAM data 1 input or output (bit 11) SDRAM data 1 input or output (bit 4) SDRAM data 1 input or output (bit 12) SDRAM data 1 input or output (bit 3) SDRAM data 1 input or output (bit 13) SDRAM data 1 input or output (bit 2) supply voltage for pad ring SDRAM data 1 input or output (bit 14) SDRAM data 1 input or output (bit 1) SDRAM data 1 input or output (bit 15) SDRAM data 1 input or output (bit 0) read command 1 output read command 1 input ground for pad ring 81 MHz SDRAM clock memory input 81 MHz SDRAM clock return path output supply voltage for pad ring read command 2 input read command 2 output SDRAM data 2 input or output (bit 0) SDRAM data 2 input or output (bit 15) SDRAM data 2 input or output (bit 1) SDRAM data 2 input or output (bit 14) ground for pad ring SDRAM data 2 input or output (bit 2) SDRAM data 2 input or output (bit 13) SDRAM data 2 input or output (bit 3) SDRAM data 2 input or output (bit 12) SDRAM data 2 input or output (bit 4) SDRAM data 2 input or output (bit 11) supply voltage for pad ring SDRAM data 2 input or output (bit 5) SDRAM data 2 input or output (bit 10) SDRAM data 2 input or output (bit 6) ground for core logic supply voltage for digital core logic 10
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
SYMBOL SDRAM_DATA2(9) SDRAM_DATA2(7) SDRAM_DATA2(8) VSS SDRAM_WE2 SDRAM_CAS2 SDRAM_RAS2 SDRAM_UDQ2(0) SDRAM_UDQ2(1) VDD SDRAM_ADDR2(8) SDRAM_ADDR2(9) SDRAM_ADDR2(11) SDRAM_ADDR2(7) SDRAM_ADDR2(10) SDRAM_ADDR2(6) VSS SDRAM_ADDR2(0) SDRAM_ADDR2(5) SDRAM_ADDR2(1) SDRAM_ADDR2(4) SDRAM_ADDR2(2) SDRAM_ADDR2(3) VDD TDI TDO TMS TRST TCK VDD(AN) IDUMP2 B G AVDD3 R AVDD2 Y/CVBS C/CVBS IDUMP1 AVSS RSET 2000 Jan 31
PIN 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
TYPE(1) I/O I/O I/O S O O O O O S O O O O O O S O O O O O O S I O/Z I I I S - - - S - S - - - S -
DESCRIPTION SDRAM data 2 input or output (bit 9) SDRAM data 2 input or output (bit 7) SDRAM data 2 input or output (bit 8) ground for pad ring SDRAM write enable 2 output SDRAM column address 2 output SDRAM row address strobe 2 output SDRAM write mask 2 (0) output SDRAM write mask 2 (1) output supply voltage for pad ring SDRAM address 2 output (bit 8) SDRAM address 2 output (bit 9) SDRAM address 2 output (bit 11) SDRAM address 2 output (bit 7) SDRAM address 2 output (bit 10) SDRAM address 2 output (bit 6) ground for pad ring SDRAM address 2 output (bit 0) SDRAM address 2 output (bit 5) SDRAM address 2 output (bit 1) SDRAM address 2 output (bit 4) SDRAM address 2 output (bit 2) SDRAM address 2 output (bit 3) supply voltage for pad ring boundary scan test data input; note 2 boundary scan test data output; note 2 boundary scan test mode select input; note 2 boundary scan test data input; note 2 boundary scan test clock input 3.3 V supply for analog blocks(PLL) analog sink 2 analog video (blue) analog video (green) analog supply 3 analog video (red) analog supply 2 analog luminance/analog composite video analog chrominance/analog composite video analog sink 1 analog supply ground analog reference 11
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
SYMBOL AVDD1 VSS GRPH VS HS CP27 VDD YUV(0) VSS(CO) VDD(CO) YUV(1) YUV(2) YUV(3) YUV(4) YUV(5) YUV(6) YUV(7) VSS SPDIF WS WB SD SCK FSCLK RESET TTX TTXRQ/CPU_SEL(1) VDD IRQ(1) IRQ(0) V_REQ A_REQ AUDDEN A_DATA AV_DATA(0) AV_DATA(1) AV_DATA(2) AV_DATA(3) AV_DATA(4) AV_DATA(5) AV_DATA(6) 2000 Jan 31
PIN 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161
TYPE(1) S S O/Z I/O I/O O S I/O S S I/O I/O I/O I/O I/O I/O I/O S O/Z O/Z O/Z O/Z O/Z I/O I I I/O S O/Z O/Z O/Z O/Z I I I I I I I I I analog supply 1 ground for pad ring
DESCRIPTION
indicator for graphics information output; note 2 vertical synchronization input or output; note 2 horizontal synchronization input or output; note 2 27 MHz video presentation clock output; note 2 supply voltage for pad ring YUV video input or output (bit 0);at 27 MHz; note 2 ground for core logic supply voltage for digital core logic YUV video input or output (bit 1); at 27 MHz; note 2 YUV video input or output (bit 2); at 27 MHz; note 2 YUV video input or output (bit 3); at 27 MHz; note 2 YUV video input or output (bit 4); at 27 MHz; note 2 YUV video input or output (bit 5); at 27 MHz; note 2 YUV video input or output (bit 6); at 27 MHz; note 2 YUV video input or output (bit 7); at 27 MHz; note 2 ground for pad ring digital audio output; note 2 word select output; note 2 word begin output; note 2 serial audio data output; note 2 serial audio clock output; note 2 256 or 384 x fs clock input or output; hard reset input; note 2 teletext data input; note 2 teletext data request or CPU data interface selection (1); note 2; note 3 supply voltage for pad ring individually maskable interrupt (1) output; note 2 individually maskable interrupt (0) output; note 2 video data request output; note 2 audio data request output; note 2 byte synchronisation of serial audio input A_DATA; note 2 MPEG audio stream serial port input; note 2 MPEG stream port input (bit 0); note 2 MPEG stream port input (bit 1); note 2 MPEG stream port input (bit 2); note 2 MPEG stream port input (bit 3); note 2 MPEG stream port input (bit 4); note 2 MPEG stream port input (bit 5); note 2 MPEG stream port input (bit 6); note 2 12
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
SYMBOL AV_DATA(7) ERROR A_STROBE V_STROBE VSS (gate input) CPU_SEL(0) CLK VSS SIZ(1) SIZ(0) ADDRESS(20) ADDRESS(19) ADDRESS(18) ADDRESS(17) ADDRESS(16) ADDRESS(15) ADDRESS(14) ADDRESS(13) ADDRESS(12) ADDRESS(11) VSS(CO) VDD(CO) VDD ADDRESS(10) ADDRESS(9) ADDRESS(8) ADDRESS(7) ADDRESS(6) ADDRESS(5) ADDRESS(4) ADDRESS(3) ADDRESS(2) ADDRESS(1) ADDRESS(0) R/W DMA_RDY DMA_DONE DMA_REQ DMA_ACK CSRG CSSD/ADDRESS(21) 2000 Jan 31
PIN 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
TYPE(1) I I I I S I I S I I I I I I I I I I I I S S S I I I I I I I I I I I I O/Z I I/O I I I
DESCRIPTION MPEG stream port input (bit 7); note 2 flag for bitstream error; note 2 audio data strobe for AV_DATA and A_DATA inputs; note 2 video data strobe for AV_DATA and A_DATA inputs; note 2 ground for pad ring CPU data interface selection (0) input; note 2; note 3 27 or 40.5 MHz clock input; note 2 ground for pad ring size of data on bus DATA (1) input; note 2 size of data on bus DATA (0) input; note 2 CPU address input (bit 20); note 2 CPU address input (bit 19); note 2 CPU address input (bit 18); note 2 CPU address input (bit 17); note 2 CPU address input (bit 16); note 2 CPU address input (bit 15); note 2 CPU address input (bit 14); note 2 CPU address input (bit 13); note 2 CPU address input (bit 12); note 2 CPU address input (bit 11); note 2 ground for core logic supply voltage for digital core logic supply voltage for pad ring CPU address input (bit 10); note 2 CPU address input (bit 9); note 2 CPU address input (bit 8); note 2 CPU address input (bit 7); note 2 CPU address input (bit 6); note 2 CPU address input (bit 5); note 2 CPU address input (bit 4); note 2 CPU address input (bit 3); note 2 CPU address input (bit 2); note 2 CPU address input (bit 1); note 2 CPU address input (bit 0); note 2 read or write input; note 2 DMA ready output; note 2 DMA end input; note 2 DMA request input or output; note 2 DMA acknowledge input; note 2 chip select for control register access input; note 2 chip select for SDRAM access or CPU address (bit 21) input; note 2 13
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
SYMBOL DATACK DS/TS DATA(0) DATA(1) DATA(2) DATA(3) Notes
PIN 203 204 205 206 207 208
TYPE(1) O/Z I I/O I/O I/O I/O
DESCRIPTION data acknowledge output; note 2 data strobe or transfer start input; note 2 CPU data input or output (bit 0); note 2 CPU data input or output (bit 1); note 2 CPU data input or output (bit 2); note 2 CPU data input or output (bit 3); note 2
1. Pin type abbreviations: I = Input, O = Output, I/O = Input or Output, O/Z = high impedance Output and S = Supply voltage. 2. 5 V tolerant outputs swing between VSS and VDD. 5 V tolerant inputs can receive signals swinging between VSS and 3.3 V or VSS and 5 V. 3. Signal CPU_SEL(1) is used only after a global hardware reset is applied on external input line RESET for determining the type of the microcontroller connected to SAA7215; SAA7216; SAA7221 and therefore apply the proper communication protocol. This microcontroller type must be given by means of weak pull-up or pull-down externally connected to CPU_SEL(1). During normal operation, the pin TTXRQ/CPU_SEL(1) is used for implementing the Teletext Data Request protocol and must not be disturbed by the microcontroller type setting.
2000 Jan 31
14
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
Pin configuration
SAA7215; SAA7216; SAA7221
208
handbook, halfpage
157
1
156
SAA7215HS SAA7216HS SAA7221HS
52 105
53
104
FCE351
Fig.4 Pin configuration.
2000 Jan 31
15
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
Pinning table (listed by function) PIN 166 168 145 162 161 160 159 158 157 156 155 154 153 164 165 152 151 163 142 143 140 141 139 144 126 137 136 135 134 133 132 131 128 125 124 123 114 112 111 116 CLK RESET AV_DATA(7) AV_DATA(6) AV_DATA(5) AV_DATA(4) AV_DATA(3) AV_DATA(2) AV_DATA(1) AV_DATA(0) A_DATA AUDDEN A_STROBE V_STROBE A_REQ V_REQ ERROR SD SCK WS WB SPDIF FSCLK CP27 YUV(7) YUV(6) YUV(5) YUV(4) YUV(3) YUV(2) YUV(1) YUV(0) HS VS GRPH R/CVBS G B Y/CVBS SYMBOL VSS (gate input) TYPE(1) S I I I I I I I I I I I I I I O/Z O/Z I O/Z O/Z O/Z O/Z O/Z I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O/Z - - - - - - - - - - - - - - - - - - - 3 mA 3 mA - 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA - - - - 16 DRIVE
SAA7215; SAA7216; SAA7221
VOLTAGE 0V 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant - - - - -
ACTIVITY rising edge low level direct level direct level direct level direct level direct level direct level direct level direct level low level high level program level program level program level program level program level direct level edge direct level direct level direct level edge rising edge direct level direct level direct level direct level direct level direct level direct level direct level program level program level high level analog analog analog analog
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN 117 53 51 48 46 44 41 39 37 38 40 42 45 47 49 52 54 28 24 29 30 25 23 20 18 16 17 19 21 33 34 35 32 59 58 55 56 64 66 69 71 C/CVBS
SYMBOL SDRAM_DATA1(15) SDRAM_DATA1(14) SDRAM_DATA1(13) SDRAM_DATA1(12) SDRAM_DATA1(11) SDRAM_DATA1(10) SDRAM_DATA1(9) SDRAM_DATA1(8) SDRAM_DATA1(7) SDRAM_DATA1(6) SDRAM_DATA1(5) SDRAM_DATA1(4) SDRAM_DATA1(3) SDRAM_DATA1(2) SDRAM_DATA1(1) SDRAM_DATA1(0) SDRAM_ADDR1(11) SDRAM_ADDR1(10) SDRAM_ADDR1(9) SDRAM_ADDR1(8) SDRAM_ADDR1(7) SDRAM_ADDR1(6) SDRAM_ADDR1(5) SDRAM_ADDR1(4) SDRAM_ADDR1(3) SDRAM_ADDR1(2) SDRAM_ADDR1(1) SDRAM_ADDR1(0) SDRAM_RAS1 SDRAM_CAS1 SDRAM_WE1 SDRAM_UDQ1 CP81M CP81MEXT READ_OUT1 READ_IN1 SDRAM_DATA2(15) SDRAM_DATA2(14) SDRAM_DATA2(13) SDRAM_DATA2(12)
TYPE(1) - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O I O I I/O I/O I/O I/O -
DRIVE - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 8 mA - 2 mA - 2 mA 2 mA 2 mA 2 mA 17
VOLTAGE
ACTIVITY analog direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level low level low level low level direct level edge edge low level low level direct level direct level direct level direct level
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN 73 76 80 82 81 77 75 72 70 68 65 63 92 94 91 90 93 95 98 100 102 101 99 97 86 85 84 88 87 62 61 147 167 146 14 13 12 11 10 9 7
SYMBOL SDRAM_DATA2(11) SDRAM_DATA2(10) SDRAM_DATA2(9) SDRAM_DATA2(8) SDRAM_DATA2(7) SDRAM_DATA2(6) SDRAM_DATA2(5) SDRAM_DATA2(4) SDRAM_DATA2(3) SDRAM_DATA2(2) SDRAM_DATA2(1) SDRAM_DATA2(0) SDRAM_ADDR2(11) SDRAM_ADDR2(10) SDRAM_ADDR2(9) SDRAM_ADDR2(8) SDRAM_ADDR2(7) SDRAM_ADDR2(6) SDRAM_ADDR2(5) SDRAM_ADDR2(4) SDRAM_ADDR2(3) SDRAM_ADDR2(2) SDRAM_ADDR2(1) SDRAM_ADDR2(0) SDRAM_RAS2 SDRAM_CAS2 SDRAM_WE2 SDRAM_UDQ2(1) SDRAM_UDQ2(0) READ_OUT2 READ_IN2 TTXRQ/CPU_SEL(1) CPU_SEL(0) TTX DATA(15) DATA(14) DATA(13) DATA(12) DATA(11) DATA(10) DATA(9)
TYPE(1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O I I/O I I I/O I/O I/O I/O I/O I/O I/O
DRIVE 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA - 3 mA - - 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 18 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
VOLTAGE
ACTIVITY direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level low level low level low level direct level direct level low level low level direct level level direct level direct level direct level direct level direct level direct level direct level direct level
5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN 6 5 4 3 2 208 207 206 205 172 173 174 175 176 177 178 179 180 181 185 186 187 188 189 190 191 192 193 194 195 170 171 201 202 204 196 203 199 200 197 198 DATA(8) DATA(7) DATA(6) DATA(5) DATA(4) DATA(3) DATA(2) DATA(1) DATA(0)
SYMBOL
TYPE(1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I I I I I I I I I I I O/Z I/O I O/Z I
DRIVE 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA 6 mA - - - - - - - - - - - - - - - - - - - - - - - - - - - 6 mA 3 mA - 3 mA - 19
VOLTAGE 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant
ACTIVITY direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level direct level low level low level low level direct level low level program level program level program level program level
ADDRESS(20) ADDRESS(19) ADDRESS(18) ADDRESS(17) ADDRESS(16) ADDRESS(15) ADDRESS(14) ADDRESS(13) ADDRESS(12) ADDRESS(11) ADDRESS(10) ADDRESS(9) ADDRESS(8) ADDRESS(7) ADDRESS(6) ADDRESS(5) ADDRESS(4) ADDRESS(3) ADDRESS(2) ADDRESS(1) ADDRESS(0) SIZ(1) SIZ(0) CSRG CSSD/ADDRESS(21) DS R/W DTACK DMA_REQ DMA_ACK DMA_RDY DMA_DONE
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN 149 150 104 105 106 108 107 121 115 113 118 110 120 119 27 79 130 183 8 22 36 50 60 74 89 103 127 148 184 109 26 78 129 182 1 15 31 43 57 67 83 IRQ(1) IRQ(0) TDI TDO TMS TCK TRST AVDD1 AVDD2 AVDD3 IDUMP1 IDUMP2 RSET AVSS VDD(CO) VDD(CO) VDD(CO) VDD(CO) VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD(AN) VSS(CO) VSS(CO) VSS(CO) VSS(CO) VSS VSS VSS VSS VSS VSS VSS
SYMBOL
TYPE(1) O/Z O/Z I O/Z I I I S S S - - - S S S S S S S S S S S S S S S S S S S S S S S S S S S S
DRIVE 3 mA 3 mA - 3 mA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20
VOLTAGE 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant 5.0 V tolerant - - - - - - - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V
ACTIVITY program level program level direct level direct level direct level edge low level - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN 96 122 138 169 Notes VSS VSS VSS VSS
SYMBOL
TYPE(1) S S S S - - - -
DRIVE 0V 0V 0V 0V
VOLTAGE - - - -
ACTIVITY
1. Pin type abbreviations: I = Input, O = Output, I/O = Input or Output, O/Z = high impedance Output and S = Supply voltage.
2000 Jan 31
21
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
APPLICATION INFORMATION
SAA7215; SAA7216; SAA7221
handbook, full pagewidth
16-Mbit SDRAM
16 data UART PIO I2C 12 addr 4 ctrl 5
16-Mbit SDRAM (OPTIONAL)
12 addr 16 data
ctrl
2
HS, VS CP27 CCIR-656 GRPH Y/C/CVBS RGB
1 TS-in (pktdata) AV data 8 2 2
SAA7214 (T-MIPS)
Strobe IRQ ERROR
SAA7215 SAA7216 SAA7221 MPEG-2AVGD DECODER
8 1 2 3 6
Audio DAC
13.5 MHz 40.5 MHz Extension bus
16 data
21 addr
DS R/W CSSD CSRG
DTACK
EPROM
DRAM
FLASH
FCE111
Fig.5 Set-top box example.
2000 Jan 31
22
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PACKAGE OUTLINE
SAA7215; SAA7216; SAA7221
SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT316-1
c
y
X
A
156 157 105 104
ZE
e E HE A2 A1 (A 3) Lp L pin 1 index
208 53 52
A
wM bp
detail X
1
e
bp D HD
wM
ZD B
vM A
vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.10 A1 0.50 0.25 A2 3.6 3.2 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD 30.9 30.3 HE 30.9 30.3 L 1.3 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.39 1.11 1.39 1.11 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT316-1 REFERENCES IEC JEDEC MS-029 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-25
2000 Jan 31
23
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
SAA7215; SAA7216; SAA7221
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Jan 31
24
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not REFLOW(1)
2000 Jan 31
25
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
NOTES
SAA7215; SAA7216; SAA7221
2000 Jan 31
26
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
NOTES
SAA7215; SAA7216; SAA7221
2000 Jan 31
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp28
Date of release: 2000
Jan 31
Document order number:
9397 750 05379

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